1. Field of Invention
The present invention relates to a structure and method of fabricating a capacitor of a semiconductor memory. More particularly, the present invention relates to a structure and method of fabricating a stacked capacitor of a Dynamic Random Access Memory (DRAM).
2. Description of Related Art
A semiconductor memory, such as a DRAM, mainly consists of a transistor and a capacitor. Therefore, the improvement in the efficiency of the two tends to be the direction in which technology is developing.
When the semiconductor enters the deep sub-micron process, the size of the device becomes smaller. For the conventional DRAM structure, this means that the space used by the capacitor becomes smaller. Since computer software gradually becoming huge, more memory capacity is required. In the case where it is necessary to have a smaller size with sufficient memory capacity, the conventional method of fabricating the DRAM capacitor has to change in order to fulfill the requirements of the trend.
There are two approaches at present for reducing the size of the capacitor while increasing its capacitance. One way is to select a dielectric layer with a high dielectric constant, and the other is to increase the surface area of the lower electrode of the capacitor. For the first method. high dielectric constant (k) materials, for example, Ta.sub.2 O.sub.5 with a dielectric constant of about 25 and BaTiO.sub.3 with a dielectric constant well above five hundred, are becoming popular.
However, there are two main types of capacitors that increase the surface area of the lower electrode of the capacitor. These are the deep trench type and the stacked type, wherein the deep trench type capacitor is formed by digging out a trench with a depth of 6-7 .mu.m.
The stacked capacitor is a principal method of fabricating the conventional semiconductor capacitor. Most of the semiconductor manufacturers, such as NEC in Japan and Samsung, in Korea have developed advanced technology which involves a size below 0.25 .mu.m with a megabit (Mb) capacity for such a capacitor.
As the material having a high dielectric constant is used in the stacked capacitor, the material for the conventional upper and lower electrodes also need to be gradually replaced so as to improve the performance of the capacitor. The structure known as a metal-insulator-metal (MIM) structure has a low interfacial reaction to enhance the performance of the capacitor, and therefore it has become an important topic of research for the semiconductor capacitor in the future.
However. the conventional metal-insulator-polysilicon (MIS) capacitor which uses doped polysilicon as the lower electrode, can be formed into a hemispherical grain (HSG). crown, or fin electrode by a polysilicon storage node. This increases the surface area of the lower electrode of the capacitor and enhances the capacitance.
But for the MIM capacitor, it is difficult to transform uniform metal film into the shape of hemispherical grain, crown, or fin with the culrent semiconductor manufacturing technology.